Full-wave differential control circuit employing single saturable core transformer



March 30, 1965 D. E. MEIER 3,176,243

FULL-WAVE DIFFERENTIAL CONTROL CIRCUIT EMPLOYING SINGLE SATURABLE CORE TRANSFORMER 5 Sheets-Sheet 1 Filed April 2, 1962 PRIOR ART DC CONTROL VOLTAGE, 6c

mi r! INVENTOR.

DON E. MEIER D. E. MEIER 3,176,243

March 30, 1965 FULL-WAVE DIFFERENTIAL CONTROL CIRCUIT EMPLOYING SINGLE SATURABLE CORE TRANSFORMER 3 Sheets-Sheet 2 Filed April 2. 1962 INVENTOR.

DON E. MEIER March 30, 1965 D. E. MEIER 3,176,243

FULL-WAVE DIFFERENTIAL CONTROL CIRCUIT EMPLOYING SINGLE SATURABLE CORE TRANSFORMER Filed April 2, 1962 3 Sheets-Sheet 3 INVENTOR.

l7 DON E. MEIER United States Patent FULL-WAVE DIFFERENTIAL CONTRGL CIR- CUET EWLOYING SINGLE SATURABLE CORE TRANSFURMER Don E. Meier, Marion, Iowa, assiguor to Collins Radio Company, Cedar Rapids, Iowa, a corporation of Iowa Filed Apr. 2, 1962, er. No. 184,357 6 Claims. (Cl. 331-413) This invention relates generally to differential control circuitry and more particularly to a type of full wave differential control employing saturable current transformer techniques in conjunction with transistor switching.

The invention is basically embodied in the provision of a three-wire output of the double ended or two-phase type such as might be used for controlling a servo motor or other devices requiring a differential output.

Numerous circuits are employed in the art which utilize transistor switching techniques in conjunction with saturable magnetic cores and such circuits are widely employed for control of reversible motors, for example. The present invention resides in the provision of a two-phase or double-ended signal development employing a minimum of circuitry so as to reduce weight and volumetric requirements as compared with known circuitry. The general approach, as applied herein to motor control, for example, is the provision of a double-ended output which introduces an unbalance in the average flux developed in motors to produce motor rotation in either direction.

The present invention is featured in the provision of means employing a single saturable core member in conjunction with switching transistors and a direct current voltage supply source to obtain a load driving source of the double-ended or fullwave type. The minimum circuitry uniquely enables a differential pulse Width modulation by novel control of both the on and off-time portions of switching duty cycles.

Additional features of the present invention are the provision of developing a double-ended or full-wave output signal which is differentially controllable by variation of the control circuit impedance as reflected into the load circuitry and in means whereby this differential control may be attained by variation of physical impedance parameters per se or by electronic variation of said reflected impedance in response to a direct current voltage control source.

These and other objects and features of the present invention will become apparent upon reading the following description in conjunction with the accompanying drawings in which:

FIGURES 1(a) and 1(b) are a schematic representation of a prior art control circuitry of a related type, and an operational diagram thereof;

FIGURES 2(a) and 2(1)) are a diagrammatic illustration of the output Wave forms of the circuit of FIGURE 1(a) as a function of variation in put parameters;

FIGURES 3 (a) and 3 (b) are an operational schematic and equivalent circuit concerning operational aspects of the circuit of FIGURE 1(a);

FIGURE 4 is a schematic representation of an embodiment of the present invention;

FIGURE 5 is a diagrammatic representation of operational waveforms of the circuitry of FIGURE 4;

FIGURES 6 and 7 are schematic embodiments of types of output circuitry controllable by the circuitry of the invention;

FIGURES 8(a) and 8(1)) represent a schematic variation and modification of a portion of the circuitry of FIGURE 4;

FIGURE 9 represents a further embodiment of the present invention utilizing D.C. voltage control, and

3,176,243 Patented Mar. 30, 1965 FIGURE 10 represents a further embodiment of the invention employing drive current control technique.

The present invention relates to circuitry by which twophase control may be obtained utilizing but a single saturable core in conjunction with switching transistors whereby differential control of a controlled member such as, for example, a split-phase direct current motor, may be obtained by differential control of the pulse widths of differential output drive pulses. The present invention may best be understood by a consideration of a prior art technique disclosed by R. E. Morgan and described in AIEE Communications and Electronics, Volume 77, page 558, in an article entitled, Saturable Current Transformer and Transistor Switch. The reference article describes the use of a current transformer in series with a power transistor, a D.C. supply, and a load. This circuitry was presented for use as a single-ended control of a load and might be basically defined as a square wave oscillator with frequency controlled by a D.C. input to the current transformer. The present invention relates generally to this prior art circuitry and certain operational aspects of the circuitry of the present invention may be comprehended by a discussion of the operational aspects of the Morgan circuit as it relates to single ended control. The present invention stems from an insight suggested by a study of the operational aspects of the prior art circuit with application to two-phase control circuitry, while retaining the simplified approach of utilizing but a single saturable core.

The basic amplifier circuit disclosed by Morgan in the above referenced article is illustrated in FIGURE 1A and the approximate characteristic of the core member is shown in FIGURE 18. With reference to FIGURE 18, note is made of the finite slope of the core characteristic in the saturation regions which serve as a good approximation for HY Mn 80, the core material utilized in constructed embodiments of the present invention.

With reference to FIGURE 1, assume initially that flux is at F and a small amount of emitter to collector leakage current moves the flux from F to A. This causes a small voltage, e to be induced positive at the dot. This voltage, e causes base current to flow in Q and Q starts to turn on, increasing i to the magnetizing level at B. The net effect is a regenerative action and Q turns on rapidly. A constant voltage e =Ei R is applied to the primary causing a flux excursion from B to C. This excursion defines the on time and is determined by e the number of primary turns, and the total change in flux. When the flux level reaches point C, 2 drops to zero, Q begins to shut off and i decreases. During the decrease of z' flux moves in the direction C to D on the B-H loop, experiencing a change in slope of the flux-time characteristic. This results in an induced voltage, e negative at the dot, that completely biases Q to the olf condition. This again is a regenerative action and Q shuts off rapidly once saturation is reached. With Q shut oif, fiux comes to rest at point x, corresponding to zero magnetizing force and the reset period is ready to begin.

In order to reset the core an external reverse magnetizing force H must be applied. This is done by applying a control voltage 2 to the secondary. With application of a i quickly builds up to a magnetizing current corresponding to point E on the flux loop. The off time interval lasts during the flux excursion from E to F. The time of this interval is determined by c the number of secondary turns, and the total change in flux. The off time can be controlled by varying e Large values of (2 result in a short off time while small values cause a long off time. A limiting value of e is reached when e reduces to a point where i =e /R corresponds to a magnetizing force It. iting value, the flux never reaches F and begins to traverse minorloops as shown. This results in an increase of oscillator frequency. It can be seen that the circuit operates on the principle of constant on time andvariable olf time. A typical set of output waveforms is shown in FIGURE 2a with the corresponding control characteristic appearing in FIGURE 2b.

The original circuitry of FIGURE -1 operates on the principle of an output pulse waveform having constant on time with oft time varied as a function of the input control voltage e As previously discussed, the circuitry of the present invention provides, by contradistinction, a double-ended or full-wave output with provision for difierential control through variation of boththe on and on times in a differential manner. As means for gain ing insight into the operational aspects of the present invention a mathematical analysis of the effects of impedance control as it applies to either the on or oflf times is herein presented. For this purpose, analysis is made in conjunction with the single-ended prior art circuitry as follows:

A simplified schematic of the circuit during the conduction period of Q is shown in FIGURE 3w. saturation resistance of Q has been taken as zero'and the secondary circuit consists of a control resistance, R If desirable it can be considered that Q saturation resistance is lumped with R and that Q base circuit resistance is lumped with R The latter becomes important in actual designs where an external base resistor is. used. The corresponding equivalent circuit is shown in FIG-' URE 3b. Note that core losses have been neglected. This may not be a valid assumption at the higher operating frequencies.

The voltage applied to the primary winding, 2 is defined as The 7 For values of c less than this lime =N g ltlf where e is in volts and is in maxwells per second and the voltage of self induction, e carries a minus sign. The assumption of a linear slope (FIGURE 1b), is carried over to this derivation so that the time interval involved can be written as At=N,,% 10- (2) Solving for e in terms of circuit parameters? from which E e R 1.

The currents may be equated as:

Equating (4) and (5) lations.

- I 4 The general expression for pulse width control results from combining Equations 2 and 7:

Where values of flux density and elfective cross sectional area of the core. I

%)2 R R. Equation 8 can be rewritten:

i N A 10" R At (10) (til In a majority of designs attempted, the above relationship held true and Equation 10 was used. Measured values of At agreed quite well with initial design calcu- The control that R exhibits over At is more apparent in Equation. 10 than it is in Equation 8. A number of experiments were conducted using single phase or single ended amplifiers with both voltage and resistance control in conjunction with resistive and motor loads to verify the foregoing design equations.

A first embodiment of a full-wave differential control drive circuit utilizing a single core and a direct current voltage source is illustrated schematically in FIGURE 4.. With reference to FIGURE 4 a single core member 12.has wound thereon a first primary winding 13, one end of which is connected to the positive terminal of' a direct current voltage source .19. 'The other end 'of primary winding 13 is connected to the emitter of switching transistor 10 and to one end of a cooperating secondary winding 15, the other endof secondary winding 15 being connected through a variable resistance member 18 to the base of transistor 10. Windings 13 and 15 are Wound with opposite polarization as indicated by the respective dot configurations. The collector element of transistor 10 is connected through a resistor 20 to a first output terminal 22.- The negative terminal of the direct current voltage 19 is connected to a second or common output terminal 23.

The single core member 12 has additionallyfwound thereon a second set of windings comprising a primary winding 14, one end of which is connected to the positive terminal of direct current voltage source 19 and the other end of which is connected to the emitter of a second switching'transmitter 11 and additionally to one end of a cooperating secondary winding 16. The other end of secondary winding 16 is connected through a second variable resistance member 17 to the base of transistor 11. Windings 14 and.16 are wound with opposite polarization as indicated by the respective dot configuration and each ofthe first and second primary windings and first and second secondary windings are seen to be like wound or like polarized. It is further to be noted that oppositely polarized ends of the secondary windings 15 and 16 are connected through the associated resistance members 18 and transistor.

amass-s 17 to the switching transistors and that oppositely polarized ends of primary windings 13 and 14 are connected in common to the direct current voltage source 19 and to the emitters of the associated transistors. The collector element of transistor 11 is connected through a resistance 21 to a third output terminal 24. A three terminal resistive load is shown connected to the three wire double ended output 22, 23, 24 in the form of resistance members 25 and 26 connected respectively between output terminals 22 and 24 and the common output terminal 23.

In operation, the circuitry of FIGURE 4, assuming balanced conditions including equal settings of resistance members 17 and 18, operates essentially as a free running oscillator with equal on and off times such that the net output e is zero. As indicated by Equation 10, above, the nominal frequency of oscillation is determined by the impedances reflected into the load circuit. Resistances 17 and 18 are each seen to be in series with the emitter-tobase resistance of transistors 10 and 11. Each of the symmetrical halves of the circuitry of FIGURE 4 operates in a manner defined by the above defined equations and, due to the respective polarization of the associated core windings, transistors 10 and 11 are alternately conductive with equal time intervals At as defined in Equation 10.

Adjustment of the nominal frequency of the circuit may be obtained by varying resistances 17 and 18 in the same direction so as to impart a like efiFect on the At in Equation 10 as a function of the control resistance. With the condition of equal reflected resistances, each of the symmetrical halves of the circuit generates a. square wave with the respective differential outputs e and e being 180 out of phase. This condition may be deemed a condition of zero control. Reference is made to the waveforms of FIGURE 5 which show output voltages e 2 and the combined output voltage, e for the zero control condition and it is seen that for this condition (equal settings of resistances 17 and 18) the average D.C. component of c is zero. As mentioned above the circuit provides means for adjusting the periodicity of the output voltage waveforms by varying the variable resistances 17 and 18 together that is, simultaneously and by the same amount either increasing or decreasing these resistances.

Control conditions, either positive or negative are defined as the development of output wave forms e and e wherein the on times (the conduction periods of the associated transistor) as concerns the two waveforms vary differentially. As above mentioned, this is attained through differential variation of the variable resistances 17 and 18, that is, the simultaneous increase and decrease of the respective resistances by the same amount from a nominal value. FIGURE 5 illustrates the output wave forms for conditions of positive and negative control. Under conditions of positive control, it is seen that the output, e is positive for an appreciably longer period of time corresponding to an increased on time and the off time is decreased as compared to the zero control condition. It is further seen that under positive control condition the output Waveform e has reduced on-time and decreased otf-time by the same proportionality; the on-times being defined as the conduction periods of the associated transistors and 11 during which time it is seen that the direct current voltage source 19 is essentially developed across one of output resistors 25 and 2-6 due to the low impedance emitter to collector path of the associated For condition of positive control, the output waveform e as illustrated in FIGURE 5 is seen to have an average direct current component which is positive.

The condition defined as negative control is attained by an opposite differential variation of resistance members 17 and 18 such that the on-time in the e Waveform 'is reduced from nominal while the on-time of output waveform e is increased from nominal such that output form e has a negative average direct current component. Pulse width ratios in the order of 10 to 1 may readily be ob? tained.

The load circuit in the embodiment of FIGURE 4 is illustrated as a resistive differential load which might correspond to using the drive circuitry as a direct current amplifier providing a differential DC. output (2 as a function of differential impedance variation of resistors 17 and 13. Further examples of three-terminal loads which might be operated from the circuitry of FIGURE 4 are illustrated in FIGURES 6 and 7. FIGURE 6 represents, for example, the load as being comprised of windings 25' and 26 in place of the resistive members as connected between the output terminals 22, 23 and 24. Windings 25 and 26' might be those of a hydraulic control valve or a differential relay. FIGURE 7 illustrates the load as being that of a split field series DC). motor as it might be used in servo positioning. Each of the motor field windings 30 and 31 is connected between output terminal 22 and 24 serially with the armature 29 to the common output terminal 23 with each series connection being shunted by an appropriately polarized diode 27 or 28, the latter functioning as diverter diodes to prevent inductive voltage developed by collapse of the associated motor field from being directed into the drive circuitry. The circuitry of FIGURE 4 is very desirable as a driving source for the split field series motor as illustrated in FIGURE 7, since at its null (condition of zero control) the net D.C. current in the field windings is zero and efficiency is thereby increased. Reverse operation of the split field DC. motor as driven by the circuitry of FIGURE 4 stems from an unbalance in the average flux developed in the field windings 30 and 31 to produce a net flux under positive control conditions which is opposite to that under negative control conditions.

The embodiment of FIGURE 4 provides a three wire differential output based on differential pulse width modulation wherein the modulation is effected by differential variation of control resistances. In many applications the desired control by means of differentially varying the resistances may not be practical and it may be desirable to effect the differential control by means of an applied signal. The circuitry of FIGURE 4 may accordingly be modified to include an electronic variation of the control resistances wherein the necessary variation of resistance as reflected into the control circuit loops may be realized by appropriate variation of an input voltage. Such a modification will be further discussed.

The attainment of control as a function of an input signal necessitates a relatively minor modification of the circuitry of FIGURE 4, a portion of which is illustrated in FIGURE 8. FIGURE 8A illustrates the portion of the circuitry of FIGURE 4 upon which the modification is made. The illustrated portion shows switching transistor 10 and its relationship with control resistance 18 and windings 13 and 15 upon the core 12. The basic modification of this portion of the circuitry is illustrated in FIGURE 8B wherein it is noted that the position of the control resistance 18 has been changed and primary winding 15 is returned through the repositioned control resistance 18 to the DC. voltage supply 19, rather than to the dot end of primary winding 13 as in the basic embodiment. A comparison between the modification of FIGURE 8B and that of the basic circuitry in FIGURE 8A indicates that the operation of the circuitry is unaltered providing 0 (the voltage induced in secondary windings 15) is much greater than e (the voltage in primary windings 13). This condition may be satisfied if N (the number of turns in winding 15) are chosen to be much greater than N (the number of turns in winding 13). This condition might be satisfied by making the ratio N /N equal to 25, for example.

Bearing in mind the modification illustrated in FIG- URE 83, reference is made to the operational embodiment of FIGURE 9 wherein the basic circuit of FIGURE 4 has been appropriately modified in accordance with that suggested in FIGURE 83. In the embodiment of FIGURE 9, the control resistance 18 has been replaced with a resistance 34 in parallel with the collector to emitter resistance of a' transistor 32. Similarly, con trol resistance" 17 of FIGURE 4 has been replacediwith a resistance-35- paralleling the collector to emitter resistance'of a -tran-.

sistor 33. The base elements of'transistors 32 'and- 33 are connected through resistors'36 and 37" respectively to the positive terminal of D.C. source 19 and individual-r ly to respective terminals of a source 'offinputcontrol:

voltage. The emitters of each of the transistors 32 and 33 are connected through: a resistance 38 to thepositive. terminal of D.C. voltage source 19. Translstors 32 and v 33 thus obtain a bias voltage fromresistor 38 and bias current is limited by resistors 36 and'3 7. Controlof the circuit is introduced'by the application of the D.C. in-

put control source as applied between the base elements ofthe transistors 32 and 33. ,In-the absence of" control input voltage-a zero control situation isrealized. as,,1n

the previous embodiment since, assuming balanced COI1-;'

ditions, the control impedances in each half of the circuitry are. equal and the output is a symmetrical square wave having a zero average D.C.ias illustrated in FIG- URE 5. Differential control is realized by the application'of input control voltage across the bases of the transistors 32 and 33, the relativepolarity of whlch efiects a differential change in the collector to emitter resistances.

of transistors 32 and 33 which is reflected asa change.

of base resistance for switching transistors 10fand'. 11.- Resistances 34 and 35 shunt the collector-to emitterre-, sistance of transistors 32 and 33 to limit the maximumv resistance and prevent erratic operation. 7

- A further control embodiment in accordance with the present invention is indicated in FIGURE-10 wherein resistors 18 and 17" have been replaced by' fixed resistors and additional control circuitry has been added.-' In the embodiment of FIGURE 10 the coreJmember 12 is.pro-- vided With additional windings 40 and 41 which are likeit woundwith respect to the windings 15 and 16, as .illus-- trated. The junction between windings 40 "and 41' is. connected tothe negative terminal of a D.C. Voltage source 42 and each of the windings 40 and 41 is serially. connectedwith the collector to emitter resistance of one of transistors 44 and and a common resistive member 43 to the positive terminal of the voltagesource .42..

' The base of transistor 44 is connected tothe wiperarmQ of a potentiometer 46 across which the D.C.supply is connected." The base of transistor 45 isrconnected to the junction between equal resistors .48 and 4 9 which are;

connected across the D.C. supply.

' The embodiment of FIGURE 10 enables differential control by controlling the base' current through transistors 44 and 45 which varies the, collector to emitter resistance. of these elements. This impedance is reflected into the load circuit in accordance with Equation 10 to obtain the' desired control. Assuming the wiper arm of potentiom-.

eter 46-to becentered, the base currents of-transistors 44 and 45 are equal and the associated windings 40 and 41 induce like control such that the aforedescribed con-f dition of zero control is realized; Adjustment of 'po-.

tentiometer 46 from this centered position is seen to impart, a greater or lesser control of base current through transistor 44 as" compared to transistor 45 and, correspondingly; theassociated windings 40 and 41 introduce a differentialcontrol such that the above-described conditions of positive and negative control may be realized- The embodiment of FIGURE 1O may utilize the same D.C. control source throughout; Note that the potentiom eter-46 and the resistance voltage divider 48-50 may be'shunted across D.C. voltage 42 and that D.C. voltage: source 42 may be additionally utilized as the D.C. voltage.

source -19 illustrated in FIGURES 4 and. 9. The embodiment of FIGURE 9 requires a separate voltage source v 41 in a difierentialmanner. illustrated) causes diiferential control by effectively vary-- 'ing the "i term in Equation 10. p a "The: present invention is thus seen to provide means for developing a threewire full-wavecontrol circuit utilizing but a single saturable core member anda minimum.

of circuitry. Thefbasic embodiment of FIGURE 4 and the further embodiments of FIGURES 9 and 10 provide means whereby control may be efiected in' a varietyof 'ways to'fit'particular control applications. For example considering the control circuitry. as driving a servo motor,

.the potentiometersdn FIGURES 4 and 10 might be feedback otentiometers such as control surface position po tentiometersj n aircraft. Further, the potentiometers might be command potentiometers such ,as-the well known turn and pitch controller potentiometers utilized in autopilots. 'In a like manner, the inputcontrol voltage 1 7 of the embodimentof FIGURE 9 could-be the voltage existing at the wiper arms of such feedback or command potentiometers. In any of the described embodiments the output waveform may be filtered and used as a smooth direct current outputyoltage; may be used in applications where pulse width modulation is desired-by independent-usage of output waveformse and e and-maybe used ditferentiallyte or independently (e andleg) for various gating and switching pulses.

Although'the present invention has been described with respect to particular embodiments thereof, it is not to be further limited asrchanges might bev made therein which fall within the scope of thepresentinvention as defined in the appendedclaims. I

I claim: a

a 1'. A. differential control circuit ofthe'type producing first and second output signals differentially referenced to a common output terminal comprising first and second control circuits each comprising av like-wound control Winding on a saturable, core member common to each, of said control windings; a load circuit comprising a com-r mon'direct current voltage source including a common; terminal, first and second like-wound load windings wound; onsaid saturable core'member, said loadwindings being;

oppositely polarized with respect to said control windings,

means connecting first ends of said local windings through said-direct current voltage source to said common output terminal, the other ends of each of said load windingsi being respectively '-connected to the .emitterelements of first' and second transistors, the base elements 'of said first and second transistors being respectively connected to oppositely polarized ends of said first and second control windings, the otherends of said control windings.

- control circuits each comprising a like-wound controlv winding on a saturable core member common to each of for the D.C. control,- that is the control voltage source of FIGURE 9 must be floating.

the desired control may be effected by direct application of D.C. current to the additionalcore windings40 and I Concerning again the embodiment of FIGURE 10,-'-

said control windings, said control windings being respectively serially connected with a control resistance means.

and the emitter-base junction of' a transistor; a load circuit comprising a common direct current voltage source including a common terminal; first and secondlike-wound load windings wound on said saturable core member,

said lead windings being oppositely'polarized with respect to said control windihgsQmeans connecting first;

ends, of "said load 1 windings through said direct currentvoltagesour'ce tosaidtcommon output termihahthe other ends ofeacli of said load windingsbeing respectively con nected to the emitter element of one of said transistors,

This direct application (not the collector elements of said transistors being connected respectively to said first and second output terminals; a further pair of windings like-wound upon said common saturable core member and like-polarized with respect to said first and second control windings, differential current control means connected to each of said further pair of windings; said differential current control means including a direct current voltage source, first and second variable impedance means respectively serially connected with said direct current voltage source and one of said further pair of windings, and means for differentially varying said first and second variable impedance means.

3. Control circuitry as defined in claim 2 wherein said first and second variable impedance means comprises a further pair of transistors having the respective emitter elements thereof connected in common, said direct current voltage source connected between said common emitter junction and the junction between said further pair of control windings, the collector elements of each of said further transistors connected independently to one of the other ends of said further pair of control windings and means associated with the base elements of said further transistors to effect a variation in the respective biases thereon in a differential manner.

4. A full wave differential control circuit of the type producing first and second output signals differentially referred to a common output terminal comprising a saturable core member having wound thereon first and second secondary windings, said secondary windings being mutually like wound and collectively oppositely wound with respect to said primary windings, said primary windings being serially connected with the junction of first ends thereof connected serially through a direct current voltage supply source to said common output terminal, first and second transistors, the collector elements of each of said first and second transistors connected respectively to first and second output terminals, the emitters of each of said first and second transistors connected respectively to the other ends of each of said primary windings, the bases of said first and second transistors connected respectively to oppositely polarized first ends of said secondary windings, third and fourth transistors having collector elements respectively connected to the other ends of said secondary windings and emitter elements commonly connected to the junction between said primary windings, and means I for biasing the emitter base junction of each of said third and fourth transistors in a differential manner to effect a differential variation in the collector-emitter impedance thereof.

5. A full wave differential control circuit of the type producing first and second output signals differentially referred to a common output terminal comprising a saturable core member having wound thereon first and second like wound primary windings and first and second secondary windings, said secondary windings being mutually like wound and collectively oppositely wound with respect to said primary windings, said primary windings being serially connected with the junction of first ends thereof connected serially through a first resistor and a direct current voltage supply source to said common output terminal, first and second transistors, the collector elements of each of said first and second transistors connected respectively to said first and second output terminals, the emitters of each of said first and second transistors connected respectively to the other ends of each of said primary windings, the bases of said first and second transistors connected respectively to oppositely polarized first ends of said secondary windings, third and fourth transistors having collector elements thereof respectively connected to the other ends of said secondary windings, the emitter elements of said third and fourth transistors commonly connected to the junctionbetween said primary windings, the base elements of said third and fourth transistors respectively connected through second and third resistances to said direct current voltage supply source, and a source of direct current control voltage connected between the base elements of said third and fourth transistors.

6. Control circuitry as defined in claim 5, further comprising fourth and fifth resistances respectively connected between the collector and emitter elements of said third and fourth transistors.

References Cited by the Examiner UNITED STATES PATENTS 7/60 Davis 331-113 OTHER REFERENCES ROY LAKE, Primary Examiner.

NATHAN KAUFMAN, Examiner. 

1. A DIFFERENTIAL CONTROL CIRCUIT OF THE TYPE PRODUCING FIRST AND SECOND OUTPUT SIGNALS DIFFERNTIALLY REFERENCED TO A COMMON OUTPUT TERMINAL COMPRISING FIRST AND SECOND CONTROL CIRCUITS EACH COMPRISING A LIKE-WOUND CONTROL WINDING ON A SATURABLE CORE MEMBER COMMON TO EACH OF SAID CONTROL WINDINGS; A LOAD CIRCUIT COMPRISING A COMMON DIRECT CURRENT VOLTAGE SOURCE INCLUDING A COMMON TERMINAL, FIRST AND SECOND LIKE-WOUND LOAD WINDINGS WOUND ON SAID SATURABLE CORE MEMBER, SAID LOAD WINDINGS BEING OPPOSITELY POLARIZED WITH RESPECT TO SAID CONTROL WINDINGS, MEANS CONNECTING FIRST ENDS OF SAID LOCAL WINDINGS THROUGH SAID DIRECT CURRENT VOLTAGE SOURCE TO SAID COMMON OUTPUT TERMINAL, THE OTHER ENDS OF EACH OF SAID LOAD WINDINGS BEING RESPECTIVELY CONNECTED TO THE EMITTER ELEMENTS OF FIRST AND SECOND TRANSISTORS, THE BASE ELEMENTS OF SAID FIRST AND SECOND TRANSISTORS BEING RESPECTIVELY CONNECTED TO OPPOSITELY POLARIZED ENDS OF SAID FIRST AND SECOND CONTROL WINDINGS, THE OTHER ENDS OF SAID CONTROLS WINDINGS BEING CONNECTED THROUGH FIRST AND SECOND CONTROL RESISTANCE MEMBERS TO THE JUNCTION BETWEEN SAID OUTPUT WINDINGS, THIRD AND FOURTH TRANSISTORS, THE EMITTER-COLLECTOR JUNCTIONS OF SAID THIRD AND FOURTH TRANSISTOR RESPECTIVELY SHUNTING SAID FIRST AND SECOND CONTROL RESISTANCE MEMBERS, AND MEANS CONTROLLING TRANSISTORS IN A DIFFERENTIAL MANNER TO VARY THE EMITTER-COLLECTOR IMPEDANCE THEREOF. 